The area of field programmable gate array (“FPGA”) design is evolving at a rapid pace. The increase in the complexity of FPGA architectures means that programmable logic can now be used in far more applications than ever before. For example, newer FPGAs are steering away from the traditional “logic-only” architecture to architectures that use embedded dedicated blocks for specialized applications.
In the early days of programmable logic design, designers generally tended to choose a part based on the pin count and logic gate availability. If a design would not fit or meet timing, they would invariably choose a bigger part or a faster speed grade, since the early FPGAs were similar to each other in their basic architecture (usually an array of blocks that consisted of configurable logic and registers). The performance of a particular application was usually dependent on the flexibility of this block and of the routing resources available.
Programmable logic devices are now increasingly differentiated based on the various specialized blocks and the functionality they offer. Some of the more common features that are available are, for example: embedded DSP blocks, embedded memory blocks, efficient shift registers, and other such specialized components. Although the architecture of each FPGA family is unique and vendor specific, the basic combination of the functional blocks remains essentially the same: configurable combinatorial logic (for example, look-up tables (“LUTs”), logic elements (“LEs”), combinatorial cells (“C-cells”), and the like) plus registers and perhaps high-speed carry chain circuitry.
To account for the increased number of specialized blocks while still allowing a designer sufficient flexibility to consider various FPGA target architectures supplied from a wide variety of vendors, improved synthesis tool for implementing a design in a particular FPGA architecture are desired. In particular, improved RTL synthesis tools, which generate a gate-level netlist from a register-level circuit description (for example, from a register-transfer-level (“RTL”) description) are desired.
In order to address the challenge of trying to improve the quality of results when implementing a design in a particular FPGA target architecture, it is desirable for a designer to explore various possible FPGA implementations across a multitude of potential FPGA target architectures during the RTL synthesis process. Because RTL synthesis tool are typically bundled with a particular FPGA vendor's postsynthesis tools, RTL synthesis tools are typically constrained to that vendor's particular architecture. Therefore, it is also desirable to provide a vendor-independent FPGA synthesis environment. Furthermore, most RTL synthesis tools automatically choose how RTL operator instances are to be implemented in a particular FPGA architecture, offering the user little (if any) ability to influence the process. While a user can, in some instances, modify the RTL prior to RTL synthesis to affect such implementation decisions, the procedure of doing so is time-consuming and prone to user error. Accordingly, it is further desirable to provide an RTL synthesis tool that allows the designer to more easily assign RTL operator instances to use particular hardware resources on an FPGA target architecture and/or more easily influence the automated implementation performed by the synthesis tool. Moreover, it is desirable to quickly estimate the performance of a user's design choices and to report the impact of the design choices on the overall performance of the particular FPGA architecture being considered, including resource usage.